Schottky enhanced bias circuit

ABSTRACT

Embodiments disclosed herein relate to a bias circuit that uses Schottky diodes. Typically, a bias circuit will include a number of transistors used to generate a bias voltage or a bias current for a power amplifier. Many wireless devices include power amplifiers to facilitate processing signals for transmission and/or received signals. By substituting the bias circuit design with a design that utilizes Schottky diodes, the required battery voltage of the bias circuit may be reduced enabling the use of lower voltage power supplies.

RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.15/896,617, filed on Feb. 14, 2018 and titled “SCHOTTKY ENHANCED BIASCIRCUIT,” the disclosure of which is hereby incorporated by referenceherein in its entirety, and which is a continuation of U.S. applicationSer. No. 14/868,981, filed on Sep. 29, 2015 and titled “SCHOTTKYENHANCED BIAS CIRCUIT,” the disclosure of which is hereby incorporatedby reference herein in its entirety, and which claims priority to U.S.Provisional Application No. 62/057,485, which was filed on Sep. 30, 2014and is titled “SCHOTTKY ENHANCED BIAS CIRCUIT,” the disclosure of whichis expressly incorporated by reference herein in its entirety.

BACKGROUND Technical Field

The disclosed technology relates to bias circuits and, in particular, abias circuit for a power amplifier.

Description of Related Technology

Many devices incorporate one or more power amplifiers. A power amplifierenables a signal to be amplified by adjusting the voltage of the signal.Often, the amplification or gain factor is constrained by a power supplyvoltage.

Typically, a power amplifier will be preceded by a bias circuit. Thebias circuit can be used to set an operating voltage or current for thepower amplifier. It is often desirable for the biasing to be widebandwidth in nature. One potential issue that arises in biasing thepower amplifier is that radio frequency (RF) energy tends to leak ontothe line or circuit connection between the bias circuit and the poweramplifier. This is often a disadvantage because it can cause the bias toshift and can degrade the performance of the bias circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

Throughout the drawings, reference numbers are re-used to indicatecorrespondence between referenced elements. The drawings are provided toillustrate embodiments of the inventive subject matter described hereinand not to limit the scope thereof.

FIG. 1 illustrates a circuit diagram of an embodiment of a bias circuitwith a common collector amplifier.

FIG. 2 illustrates a circuit diagram of an embodiment of a bias circuitwith a Schottky diode.

FIG. 3 is a circuit diagram of one embodiment of a power amplifiersystem.

FIG. 4 illustrates a block diagram of a wireless device including apower amplifier module.

FIG. 5 illustrates a pair of graphs comparing the voltage at a currentsource of the bias circuits of FIG. 1 and FIG. 2.

FIG. 6 illustrates a set of graphs illustrating that a feedback loop inthe bias circuit of FIG. 2 is stabilized by an RC circuit.

FIG. 7 illustrates a logarithmic graph comparing an output impedance ofthe bias circuit of FIG. 1 to an output impedance of the bias circuit ofFIG. 2.

FIG. 8 illustrates a graph comparing the voltage generated by the biascircuits of FIGS. 1 and 2 for different current values.

FIG. 9 illustrates a graph depicting the noise performance of the biascircuits of FIGS. 1 and 2.

FIG. 10 illustrates a logarithmic graph comparing an output impedance ofthe bias circuit of FIG. 1 with an output impedance of the bias circuitof FIG. 2 as measured from a power amplifier.

FIG. 11 illustrates a graph illustrating the impact on the bias voltagefor the bias circuits of FIGS. 1 and 2 as the RF voltage signalincreases.

SUMMARY

One aspect of the present disclosure relates to a bias circuit. Thisbias circuit may include a first Schottky diode that includes a cathodeand an anode. The cathode may be in electrical communication with apower amplifier. The bias circuit may further include a field effecttransistor (FET) with a source in electrical communication with theanode of the first Schottky diode. In addition, the bias circuit caninclude a bipolar junction transistor in electrical communication withthe FET. The bipolar junction transistor may include a collector inelectrical communication with a gate of the FET and a base in electricalcommunication with the source of the FET.

In some implementations, the FET is a common-drain amplifier. In somecases, the FET is a source follower. Further, the first Schottky diodemay enable the bias circuit to operate using a voltage less than orequal to 2.5 volts. In certain embodiments, the first Schottky diodeenables the bias circuit to operate using a voltage of 1.9 volts.

In some designs, the FET and the bipolar junction form a feedback loop.In some such cases, the bias circuit may further include a frequencycompensation circuit to stabilize the feedback loop. The frequencycompensation circuit may include a resistor and a capacitor forming anRC circuit.

Moreover, the bias circuit can include a reference current source. Thereference current source may include a current source and a resistor.Moreover, the reference current source may be implemented separatelyfrom at least a portion of the bias circuit.

Some implementations of the bias circuit include a second Schottky diodein electrical communication with an emitter of the bipolar junctiontransistor. In some cases, a size of the first Schottky diode and a sizeof the second Schottky diode are selected such that a current density ofthe first Schottky diode and a current density of the second Schottkydiode match. Moreover, a size of the bipolar junction transistor may beselected to match a size of a transistor of the power amplifier.

Another aspect of the present disclosure relates to a power amplifiermodule that includes a power amplifier and a bias circuit. The biascircuit may include a first Schottky diode that may include a cathodeand an anode. The cathode can be in electrical communication with thepower amplifier. The bias circuit may further include a field effecttransistor (FET) with a source in electrical communication with theanode of the first Schottky diode. Moreover, the bias circuit canfurther include a bipolar junction transistor in electricalcommunication with the FET. This bipolar junction transistor can includea collector in electrical communication with a gate of the FET and abase in electrical communication with the source of the FET.

In some embodiments, the power amplifier module further includes areference current circuit in electrical communication with the biascircuit. This reference current circuit may be implemented in silicon.The bias circuit may be implemented using gallium arsenide. Moreover,the power amplifier module may further include a power amplifiercontroller configured to set a bias operating current of the biascircuit. In some cases, the bias circuit further includes a frequencycompensation circuit. Moreover, in some cases, the bias circuit furtherincludes a second Schottky diode in electrical communication with anemitter of the bipolar junction transistor.

Yet another aspect of the present disclosure relates to a wirelessdevice that includes a battery and a power amplifier module. The batterymay provide a voltage to a bias circuit. Further, the power amplifiermodule may include a power amplifier and the bias circuit. The biascircuit may include a first Schottky diode including a cathode and ananode. The cathode may be in electrical communication with the poweramplifier. Further, the bias circuit can include a field effecttransistor (FET) with a source in electrical communication with theanode of the first Schottky diode. In addition, the bias circuit mayfurther include a bipolar junction transistor in electricalcommunication with the FET. The bipolar junction transistor may includea collector in electrical communication with a gate of the FET and abase in electrical communication with the source of the FET.

In some embodiments, the battery supplies 2.5 volts or less to the biascircuit. Further, the power amplifier module may further include areference current circuit in electrical communication with the biascircuit. In some cases, the bias circuit further includes a secondSchottky diode in electrical communication with an emitter of thebipolar junction transistor. Moreover, in some cases, the bias circuitfurther includes a compensation circuit in electrical communicationbetween the gate of the FET and a base of the bipolar junctiontransistor.

DETAILED DESCRIPTION

One solution to the above described problem is to use an emitterfollower circuit, which is sometimes referred to as a common collectoramplifier. An example of this solution is illustrated in FIG. 1. Asillustrated in FIG. 1, an amplifier 102 (e.g., a common collectoramplifier) is positioned before the bias output node 104 that leads to apower amplifier (e.g., the power amplifier 332 of FIG. 3).

When including the common collector amplifier 102 in the circuit, the RFenergy causes the amplifier 102 to rectify. In other words, thesinusoidal waveform of the RF may be distorted since the minimum voltagemay be limited by the base-emitter junction voltage while the maximumvoltage is generally not constrained. As a result, the magnitude of theRF swing may be converted to a DC voltage shift. Thus, when the RFenergy leaking into the bias circuit is low, the voltage of base emitterjunction of the amplifier 102 typically will not have much variance.However, if the RF energy that leaks into the bias circuit 100 is high,the base emitter voltage will be reduced. So, as the average currentdrain in the power amplifier increases, the bias voltage tends todecrease. This decreasing bias may be counteracted as the RF signalswing increases and the emitter follower voltage or Vef that is providedto the power amplifier increases. This increasing Vef helps expand thebias of the power amplifier and increase the gain.

The use of the emitter follower circuit for preventing degradation ofthe performance of the bias circuit is sometimes referred to as a 2Vbesolution because the PA typically has a base-emitter voltage ofapproximately 1.2 volts and the amplifier 102 typically has abase-emitter voltage of 1.2 volts resulting in a 2.4 voltage drop acrossthe resister 106. The resistor 106 may be included for setting gaincompression characteristics of the power amplifier in communication withthe node 104. Typically, due to additional bias overhead and temperaturevariation, the voltage at the base of the amplifier 102 will beapproximately 2.6 or 2.7 volts. This voltage is typically compensatedfor by the transistors 110 and 112 by running a current, from thecurrent source 114, through the transistors 110 and 112 that enables thepower amplifier to be biased at the 2Vbe voltage. Thus the bias point ofthe base of the amplifier 102 is 2Vbe.

The transistors 110 and 112 are configured to function as diodes byconnecting the base and collectors together. Thus the transistors 110and 112 may form a diode stack. The transistor 112 may be furtherconfigured to match the amplifier 102. Similarly, the transistor 110 isconfigured to match the power amplifier that is in electricalcommunication with the bias circuit 100 at the node 104. Matching thetransistor 112 to the amplifier 102 and the transistor 110 to the poweramplifier may include matching the diode junction voltages of therespective elements. For example, using a silicon process, the diodejunction voltages may be configured to be 700 mV. For a heterojunctionbipolar transistor (HBT), the base-emitter diode junction voltage isapproximately 1.2 volts. Generally, a diode or transistor that issimilar to the transistor of the power amplifier is used such that thediode voltage or base emitter voltage is equal and tracks from wafer towafer.

Advantageously, in certain embodiments, by matching the transistor 112to the amplifier 102 and the transistor 110 to the power amplifier, theimpact of process variations during manufacture and temperature changesin the operating environment is reduced. Thus, consistent voltage andperformance may be provided by the power amplifier.

The current source 114 may be formed using a pFET, or a p-channelField-Effect Transistor. Usually a voltage of 300 mV is sufficient forthe pFET to operate. The combination of the voltage across the pFET andthe 2Vbe voltage is approximately 3 volts. Thus, it is typical to use a3.5 volt power supply with a minimum operating voltage of 3 volts.

If the voltage drops below 300 mV, the pFET will act as a triode andwill no longer operate in the active region. Further, it will bedifficult to accurately control the current generated by the currentsource 114. This is not a problem for devices with 3.5 volt batterysupplies. However, some manufacturers are working on new batterytechnologies that would operate at lower voltages including 2.5 voltsand 2.3 volts. Thus, if the power amplifier is to operate with a powersupply of 2.5 volts, and the 2Vbe bias stack is approximately 2.7 voltsfor a HBT configuration, not only is there no voltage for providing acurrent source, but the voltage is too low to generate the amplifier 102base voltage.

As noted above, the voltage using silicon is 700 mV. Thus, the 2Vbevalue for a bias circuit 100 using silicon is below 2.5 volts. However,silicon-based transistors typically do not provide as good performanceas a circuit built using HBT because, for example, silicon tends to havea lower voltage breakdown, which may limit the RF power. Further,silicon tends to exhibit lower gain and poorer power added efficiencycompared to materials used for creating HBT. Generally, HBT is createdusing gallium arsenide. However, other materials may be used, such assilicon germanium and gallium nitride. Generally, the circuits describedherein may be used for bipolar transistor types. Further, the circuitsdescribed herein could be used with silicon enabling lower voltage forapplications that do not require the improved performance of HBT. Forexample, some complementary metal oxide semiconductor (CMOS)applications may benefit from some embodiments disclosed herein becausethe diodes are often available for such applications, but the NPNtransistors may not be available. For instance, silicon BiCMOS maysupport supply voltages as low as 1V using embodiments described hereinwhile the 2Vbe bias may be limited to ˜2V.

The bias circuit 100 may further include a diode 120 and a resistor 122that functions to provide a DC bias to the emitter-follower, or commoncollector amplifier 102. Typically, the diode 120 is not a Schottkydiode, but is instead a base collector junction diode. The basecollector junction diode may be used because it generally has a lowerjunction voltage than the base emitter junction diode that may be usedin the HBT process. Further, the bias circuit 100 may be powered by avoltage supply in communication with the node 130. Usually, the voltagesupply is a battery (not shown) or other power supply of a device thatincludes the bias circuit 100, such as a mobile telephone, smartphone,tablet, video game system, television, laptop, or other computing orelectronic system. However, in some cases, the bias circuit 100 may bepowered by an alternate power supply, such as a localized power sourcethat is separate from the device battery or a wall socket that ispowering a device that includes the bias circuit 100.

The bias circuit 100 may also include a capacitor 118. This capacitor118 prevents fluctuations in the base voltage of the amplifier 102caused by the RF signal that leaks from the power amplifier onto thebias circuit 100. Often, a relatively large RF voltage (e.g., severalvolts) swing may be on node 104 as it is directly connected to the RFamplifier signal path. Thus, voltage may be conducted through resistor106, which can act as a voltage divider with the resistor 106 workingagainst the emitter impedance of the amplifier 102. The capacitor 118can serve as a RF ground for the RF frequencies preventing the RFfrequencies from altering the base voltage of the amplifier 102.

As is described further herein, one solution that reduces the requiredvoltage of the bias circuit is to use Schottky diodes. In certainembodiments, the Schottky diode can be used as a substitute for at leastsome of the transistors of the bias circuit 100. Advantageously, incertain embodiments, by reducing the required voltage of the biascircuit, the required power supply can be reduced enabling the use ofbatteries with a lower voltage. In some cases, using batteries with alower voltage enables the battery, and consequently the device to beshrunk compared to existing designs. Further, in some cases, using biascircuits that can operate at lower voltages can increase the batterylife of devices.

Example Bias Circuit with Schottky Diode

FIG. 2 illustrates a bias circuit 200 that is capable of operating atlower voltages compared to the bias circuit 100 while maintaining theperformance of the bias circuit 100. The bias circuit 200 can operatewith a battery voltage of approximately 2 volts. Thus, the bias circuit200 can be used in devices designed for 2.5 volt operation, in contrastto embodiments of the bias circuit 100.

The bias circuit 200 includes a number of circuit elements that, in someimplementations, can be equivalent to elements of the bias circuit 100.These equivalent circuit elements share common reference numeralsbetween the bias circuit 100 and the bias circuit 200. Further, the biascircuit 200 includes a number of additional circuit elements and anumber of circuit elements that substitute for corresponding elements ofthe bias circuit 100.

The bias circuit 200 includes a Schottky diode 202 and a source followeror common-drain amplifier 208, which in combination can serve as asubstitute for the amplifier 102 of the bias circuit 100. The sourcefollower may be a field effect transistor (FET), and, in some cases, maybe an n-channel device or a p-channel device, such as an NMOS or a PMOS,respectively. The amplifier 208 sources the DC current for the poweramplifier through the resistor 106 to the node 104 that is in electricalcommunication with the power amplifier. The diode 202 provides therectification functionality previously provided by the amplifier 102. Inthe bias circuit 100, the amplifier 102 is capable of both sourcing theDC current and rectifying the signal provided to the power amplifier. Inthe bias circuit 200, the functionality of the amplifier 102 is splitbetween the amplifier 208 and the diode 202. However, the drain on thebattery or voltage supply is reduced enabling the use of a smallerbattery supply.

Typically a Schottky diode has a junction voltage potential of about 0.6volts. Further, the amplifier 208 is generally an FET and may be formedusing gallium arsenide or another FET process option. Moreover, theamplifier 208 may be a depletion mode FET. With the depletion mode FET,the gate voltage is pulled below the source voltage of the transistor toturn it off. Thus, the amplifier 208 is normally on. Further, the gateand source voltage of the amplifier 208 is close to 0 and, in somecases, can even be negative. Thus, by substituting the amplifier 102with a Schottky diode and common-drain amplifier, the drain on thebattery supply voltage, not including the current source 114, can bereduced from 2.4 volts to approximately 1.8 volts assuming an HBTimplementation. Therefore, instead of the bias circuit having a 2Vbevoltage of 2.4 volts consisting of the amplifier 102 Vbe and the Vbefrom the power amplifier in electrical communication at the node 104,the bias circuit can have a 1Vbe+diode voltage of approximately 1.8volts. Moreover, the amplifier 208 may be a depletion device of about200 mV and may exhibit a gate-source voltage of <0 in the active region.As a result the maximum gate voltage of the amplifier 208 may becalculated as the sum Vd+Vbe+Vgs, wherein Vd is the diode voltage. Thus,the maximum gate voltage may be 0.7+1.4-0.2=1.9 volts. Thus, the minimumrequired battery voltage can be reduced from 2.7 volts to 1.9 volts.

In the bias circuit 100, the collector and base of the transistors 110and 112 are electrically connected together to form a pair of diodes aspart of a diode stack. However, in the bias circuit 200, the collectorand base of the transistor 110 is in electrical communication with thecommon-drain amplifier 208, which is a transistor with a gaincharacteristic and with bandwidth limitations. The collector and base ofthe amplifier 208 are connected together to form a feedback loop. Thus,if the voltage is pulled up on the base of the transistor 110 in thebias circuit 200, the collector voltage of the transistor 110 is pulleddown and the feedback has the potential to oscillate. Therefore, thebias circuit 200 includes an RC circuit to introduce frequencycompensation to stabilize the feedback loop between the transistor 110and the common-drain amplifier 208. This RC circuit includes a resistor232 and a capacitor 234. Inserting the RC circuit between the transistor110 and the amplifier 208 is sometimes referred to as a Millercompensation technique and creates what is sometimes referred to as aMiller capacitance.

In some cases, the gain across the transistor 110 of the bias circuit200 from the base to collector can be high (e.g., on the order of 300).The RC circuit compensates for the gain value by using a smallcapacitance (e.g., approximately 15 pF) that is positioned between thegate node of the amplifier 208 and ground, which creates a dominant polethat stabilizes the feedback between loop between the amplifier 208 andthe transistor 110.

As the amplifier 102 from the bias circuit 100 is replaced with thecombination of a Schottky diode 202 and common-drain amplifier 208, thetransistor 112 that matched the amplifier 102 is similarly substitutedwith a Schottky diode 210 to match the diode 202. Although thetransistor 112 is positioned between the base of the transistor 102 andthe collector of the transistor 110 in FIG. 1, the Schottky diode thatreplaced the transistor 112 may be positioned between the emitter of thetransistor 110 and ground.

In some cases, the current that flows in the power amplifier is greaterthan the current that flows in the transistor 112. As a result, it isoften desirable to use different size Schottky diodes for the diodes 202and 210. Typically, the diode 202 has a larger area than the diode 210.The area of the diodes is selected such that when a larger current flowsto the power amplifier via the node 104, the resulting voltage acrossthe diode 202 and the diode 210 is the same. In selecting the size ofthe diodes, an attempt is made to match the current density of the diode202 and the diode 210. The diode voltage may be selected by using theequation Vt*In(Id/Is). Vt is the thermal voltage across the diodejunction, which is usually 26 mV. Id represents the diode current and Isrepresents a constant that is a function of the diode area. The constantIs may change as a function of area of the junction of the diode. Thus,if the diode current Id is going to be double (e.g., 2×), then the areaof the diode should be selected to be 2× to maintain the diode voltage.Thus, in certain embodiments, the diode may be selected such that the Isvalue will scale with the current density. Therefore, in certainembodiments, the size of the diodes 202 and 210 may be selected based onthe formula for the diode voltage and a particular desired currentdensity and/or using the desire to match the current density of thediodes 202 and 210 as a constraint.

Similarly, the transistor 110 is much smaller than the effective poweramplifier array of the power amplifier. The power amplifier arraygenerally is a parallel combination of multiple devices (e.g.,transistors) resulting in a much greater current flow in the poweramplifier compared to the transistor 110. However, the transistor 110 isusually selected to have the same amount of current flowing through itas through a single transistor of the power amplifier. The base emittervoltage of the transistor may be determined as Vbe=Vt*In(Ic/Is). Ic isthe collector current through the device. Is is a constant that may varyalong with the area of the base-emitter junction. Thus, if it is desiredthat the Vbe remains constant, if the current is doubled through thedevice, then the area of the device generally needs to double to accountfor the increase in the current term of the Vbe formula. Thus, thetransistor 110 may be selected to maintain the same current per unitarea as the power amplifier.

As with the bias circuit 100, the bias circuit 200 may include a diode120 and resistor 122 that can function to provide a DC bias to theSchottky diode 202. Further, the bias circuit can include the resistor106 for setting gain compression characteristics of the power amplifierin communication with the node 104.

Similar to the bias circuit 100, the bias circuit 200 may also include acapacitor 118, which serves a similar purpose to the inclusion of thecapacitor in the bias circuit 100. The capacitor 118 of the bias circuit200 serves as a RF ground for the RF frequencies preventing the RFfrequencies from altering the voltage of the top node of the diode 202.The capacitor 118 can short or ground the top node of the diode 202 atthe RF frequencies by absorbing the RF energy. The impedance of thecapacitor can be represented by one over the capacitance times thefrequency of the signal (e.g., 1/C*Fs). Thus, as the frequency of the RFsignal increases, the impedance or effective resistance of the capacitor118 drops. As a result, the capacitor 118 shunts the current to groundas the RF signal increases and maintains the voltage of the capacitor118.

Generally, the bias circuit 200 is integrated onto the same die as thepower amplifier 332 as illustrated in FIG. 3. Advantageously, byintegrating the bias circuit 200 onto the same die as the poweramplifier 332, matching the transistor 110 to the power amplifier issimplified. In contrast, the current source 114, and associated resistor116, is often on a separate die in the power amplifier module 440.Generally, the current source 114 and the resistor 116 are included on asilicon die that provides a reference current to the power amplifier.However, in some embodiments, the current source 114 and resistor 116may be integrated on the same die as the power amplifier 332 and thebias circuit 200.

The bias circuit 200 sets the quiescent operating point for the poweramplifier 332. The quiescent operating point generally refers to the DCoperating point of the power amplifier without an RF signal. In manycases, the RF interference is used as a bias enhancement. However, theRF interference raises the required battery voltage for the biascircuit. Advantageously, the bias circuit 200 is capable of supporting alow battery voltage operation (e.g., 1.9-2 volts) while maintaining theRF bias enhancement characteristics. Further, in certain embodiments,the bias circuit 200 maintains a wide bandwidth and maintains therectification effect of the 2Vbe bias circuit 100.

Example Power Amplifier System

FIG. 3 is a circuit diagram of one embodiment of a power amplifiersystem 300. The power amplifier system 300 includes the switches 312,the antenna 314, the envelope tracker 330, the power amplifier 332, theI/O modulator 337, an envelope shaping circuit 351, a matching circuit352, an inductor 353, first and second DACs 336, 362, a power amplifiergain control circuit 361, and a power amplifier bias circuit 200.

The envelope shaping circuit 351 includes an isodistortion table 355 andthe power amplifier gain control circuit 361 includes a gain adjustmenttable 365. The envelope shaping circuit 351, the first DAC 336, and theenvelope tracker 330 are associated with an envelope tracking system ofthe power amplifier system 300. In some embodiments, the envelopetracking system may be omitted from the power amplifier system 300. Thepower amplifier gain control circuit 361, the second DAC 362, and thepower amplifier bias circuit 200 are associated with a gain controlsystem of the power amplifier system 300.

The envelope shaping circuit 351 is configured to receive an envelopesignal, and to shape the envelope signal using the isodistortion table355 to generate a shaped envelope signal, which can be used by theenvelope tracker 330 to control a voltage level of the power amplifiersupply voltage V_(CC_PA). In certain implementations, the shapedenvelope signal generated by the envelope shaping circuit 351 can be adigital signal. In such configurations, the first DAC 336 can be used toconvert the digital shaped envelope signal into an analog shapedenvelope signal, which the envelope tracker 330 can use to control thevoltage level of the power amplifier supply voltage V_(CC_PA). In oneembodiment, the isodistortion table 355 is implemented as a look-uptable, such as a programmable memory. For example, the look-up table canreceive a digital input signal indicating a voltage level of theenvelope signal, and can generate a digital output signal indicating avoltage level of the shaped envelope signal.

The power amplifier gain control circuit 361 includes an inputconfigured to receive a power feedback signal and an output configuredto generate a power control signal for the power amplifier bias circuit200 based on the gain adjustment table 365. In certain implementations,the shaped power control signal generated by the power amplifier gaincontrol circuit 361 can be a digital signal. In such configurations, thesecond DAC 362 can be used to convert the digital gain control signalinto an analog gain control signal, which can be used by the poweramplifier bias circuit 200 to generate a bias signal that can controlthe power amplifier's gain.

Thus, the gain adjustment table 365 can be used to map a power feedbacksignal to a given power amplifier bias level, thereby controlling thepower amplifier's gain. In certain implementations, the feedback signalis based in part on a sensed power of a directional coupler (not shown).At high power levels, the gain adjustment table 365 can increase thegain of the power amplifier 332, thereby relaxing a current/powerrequirement of the I/O modulator 337. Additionally, in certainimplementations, as the output power is decreased or backed-off the gainadjustment table 365 can reduce or buck the power amplifier's gain,thereby improving the efficiency of the amplifier.

In one embodiment, the gain adjustment table 365 is implemented as alook-up table, such as a programmable memory. For example, the look-uptable can receive a digital input signal indicating a voltage level of apower feedback signal and can generate a digital output signalindicating a voltage level of a bias signal.

The I/O modulator 337 is configured to receive an I signal and a Qsignal and to generate a RF signal. In certain implementations, the Iand Q signals can be provided to the I/O modulator 337 in a digitalformat. The I/O modulator 337 can be configured to receive the I and Qsignals from a baseband processor, such as the baseband system 408 ofFIG. 4, and to process the I and Q signals to generate an RF signal. Forexample, the I/O modulator 337 can include DACs configured to convertthe I and Q signals into an analog format, mixers for upconverting the Iand Q signals to radio frequency, and a signal combiner for combiningthe upconverted I and Q signals into an RF signal suitable foramplification by the power amplifier 332. In certain implementations,the I/O modulator 337 can include one or more filters configured tofilter frequency content of signals processed therein.

The power amplifier 332 includes a bipolar transistor 359, whichincludes a base configured to receive the RF signal and a bias signalfrom the power amplifier bias circuit 200. This bipolar transistor 359may be matched by the transistor 110, which in some cases may also be abipolar transistor or bipolar junction transistor (BJT). In certainimplementations, the bias signal can correspond to a base bias voltageand/or a base bias current. The bipolar transistor 359 further includesan emitter electrically connected to a ground or power low supply, and acollector configured to provide an amplified RF signal to the antenna314 through the switches 312. The collector of the bipolar transistor359 is also connected to the inductor 353, which is used to provide thepower amplifier 332 with the power amplifier supply voltage V_(CC_PA)generated by the envelope tracker 330. The inductor 353 can be used toprovide a low impedance to low frequency signal components, whilechoking or blocking high frequency signal components associated with theamplified RF signal. Alternatively, the power amplifier 332 may bepowered by a battery source or alternative power generation orprovisioning element.

The matching circuit 352 can be used to terminate the electricalconnection between output of the power amplifier 332 and the switches312. The matching circuit 352 can be used to provide a desired load lineimpedance of the power amplifier 332 at the fundamental frequency of theRF signal. In certain implementations, the matching circuit 352 can alsobe used to provide harmonic terminations, including, for example, asecond harmonic short and/or a third harmonic open.

Conventional envelope tracking systems can maintain the linearity of apower amplifier by using a shaping table that can pre-distort theinstantaneous gain of the power amplifier (AM/AM) to a substantiallyconstant gain value or isogain. By implementing the envelope trackingsystem using an isogain table, the power amplifier can be linearized anddistortion can be controlled to about the minimum value possible.

The power amplifier system 300 of FIG. 3 has been implemented based on arecognition that instantaneous isogain is not a requirement of a typicalcommunications standard and that some distortion can be permitted toimprove power added efficiency (PAE). For example, the isodistortiontable 355 can reduce current consumption by controlling the poweramplifier's supply voltage to a level sufficient to just provide therequired linearity and receive distortion, thereby providing enhancedPAE at low input power levels. Although the isodistortion table 355 candistort the RF signal, the distortion provided can be selected to beless than a maximum distortion permitted by a particular communicationsstandard. Since there is a tradeoff between distortion and linearity,the isodistortion table 355 can increase distortion but enhance PAE.

In certain implementations, the isodistortion table 355 is used to mapor convert data indicating the voltage of the envelope signal into dataindicating the voltage of the shaped envelope signal to maintainsubstantially constant distortion. The isodistortion table 355 canmaintain a substantially constant distortion in a transmit band and/or areceive band across voltage changes in the envelope signal, and can becalibrated at a particular power level. In one embodiment, theisodistortion table 355 is configured such that the power amplifier'sdistortion changes by less than about −38 decibels relative to carrier(dBc) for the transmit band and −130 decibel-milliwatt per hertz(dBm/Hz) for the receive band dB over the envelope signal's range.

The isodistortion table 355 can be calibrated for a particular powerlevel (such as an output power level) and for a particular linearity andreceive distortion. The isodistortion table 355 can operate optimallyfor the calibrated output power level but performance can fall off athigh average output power as the gain of the power amplifier 332 iscompressed to meet compression criteria. To achieve a given output powerin these conditions, the I/O modulator 337 can increase the power of theRF signal provided to the power amplifier 332. However, the I/Omodulator 337 can also work harder when increasing the RF signal'spower, and hence can significantly increase the total current of thesystem. Additionally, when the output power level of the power amplifiersystem 300 is less than that of the calibrated power level of theisodistortion table 355, the average gain of the power amplifier can behigher than a gain required by the system, which can increase thecurrent required from the battery.

To improve overall PAE, the power amplifier system 300 includes not onlythe isodistortion table 355, but also the gain adjustment table 365 forincreasing the gain of the power amplifier at high power levels toreduce a power/current requirement of the I/O modulator 337 driving thepower amplifier 332. The gain adjustment table 365 can increase or boostthe power amplifier's gain for at least a portion of the power levelsgreater than the calibration power level that the isodistortion table355 is calibrated at. Additionally, in certain implementations the gainadjustment table 365 can decrease the gain of the power amplifier atpower levels less than the calibration power level that theisodistortion table 355 is calibrated at. Although increasing the gainof the power amplifier 332 can decrease the power amplifier's efficiencyin isolation, the overall combined efficiency of the power amplifier 332and the I/O modulator 337 can be increased.

In the illustrated configuration, the gain of the power amplifier 332 isadjusted by controlling a bias of the bipolar transistor 359 using thepower amplifier bias circuit 200. For example, the power amplifier biascircuit 200 can be used to control a base current and/or base voltage ofthe bipolar transistor 359, thereby controlling the power amplifier'sgain. However, other configurations are possible. Additionally, althoughthe power amplifier system 300 is illustrated in the context of a singlestage configuration, the teachings herein are applicable to multi-stageconfigurations in which the gain of one or more of the stages isadjusted using the power amplifier bias circuit 200.

Example Wireless Device

FIG. 4 illustrates an embodiment of a wireless device 400 that mayinclude one or more power amplifier modules 440. Although the wirelessdevice 400 illustrates only one power amplifier module (PAM), it ispossible for the wireless device 400 to include a number of PAMs, eachof which may or may not be of the same configuration as PAM 440.Further, the wireless device 400 may include some of or all of thecomponents described with respect to FIG. 3 as part of power amplifiermodule 440.

The power amplifier module 440 can include a number of elements. Theseelements may include, for example, a power amplifier 332, a poweramplifier controller 461, a reference current circuit 404, and a biascircuit 200. Each of these power amplifier module elements may beimplemented on the same circuit die. Alternatively, at least some of theelements of the power amplifier module 440 may be implemented on adifferent element circuit die. Advantageously, by implementing elementson a different circuit die, different semiconductor technologies may beused for different circuit elements of the power amplifier module 440.For example, the bias circuit 200 may be implemented using galliumarsenide (GaAs) technology while the reference current circuit may beimplemented using silicon (Si).

The PAM 440 may include a power amplifier controller 461 that may beused to set and/or configure the PA 332 of the PAM 440. In some cases,the power amplifier controller 461 may include or may be replaced by thePA gain control 361. Further, certain implementations of the poweramplifier module 440 may omit the power amplifier controller 461. Forexample, the power amplifier 332 may include the power amplifiercontroller 461 on-chip or integrated with the power amplifier 332. Insome embodiments, the PAM 440 may include multiple PAs, which may sharethe PA controller 461 or which may each be associated with its own poweramplifier controller. The PA 332 can facilitate, for example, multi-bandoperation of the wireless device 400. The mode of the power amplifier332 may, in some cases, be set by the power amplifier controller 461based on a signal and/or mode selection set by the power amplifiermodule 440 or from a transceiver.

In some embodiments, the power amplifier controller 461 may set theoperating point for the PA 332 by modifying the bias circuit 200. Forinstance, the power amplifier controller 461 may set or modify a biascurrent provided by the bias circuit 200 to the PA 332.

The power amplifier 332 may include any type of power amplifier.Further, the power amplifier may be set to operate at a particularoperating point. This operating point may be configured by the biascircuit 200, which may provide a bias current and/or voltage to thepower amplifier 332.

The reference current circuit 404 may be configured to provide areference current to one or more elements of the power amplifier module440. For example, the reference current circuit 404 may provide areference current to the bias circuit 200. In some implementations, thereference current circuit 404 may include the current source 114 and theresistor 116. Further, the reference current circuit 404 may beimplemented separately from the bias circuit 200 and, in some cases, maybe implemented using a different semiconductor material and/or processthan the bias circuit 200. Alternatively, the reference current circuit404 may be of the same material as the bias circuit 200. In some suchcases, the reference current circuit 404 may be included with the biascircuit 200 as part of a single circuit die.

In some cases, the PAM 440 can receive RF signals from a transceiver 410that can be configured and operated in known manners to generate RFsignals to be amplified and transmitted, and to process receivedsignals. The transceiver 410 is shown to interact with a basebandsubsystem 408 that is configured to provide conversion between dataand/or voice signals suitable for a user and RF signals suitable for thetransceiver 410. The transceiver 410 may also be connected to a powermanagement component 406 that is configured to manage power for theoperation of the wireless device. Such power management can also controloperations of the baseband sub-system 408 and the PAM 440. It shouldalso be understood that the power management component 406 may include apower supply, such as a battery. Alternatively, or in addition, one ormore batteries may be separate components within the wireless device400.

Other connections between the various components of the wireless device400 are possible, and are omitted from FIG. 4 for clarity ofillustration only and not to limit the disclosure. For example, thepower management component 406 may be electrically connected to thebaseband subsystem 408, the PAM 440, the DSP 412, or other components414. As a second example, the baseband subsystem 408 may be connected toa user interface processor 416 that may facilitate input and output ofvoice and/or data provided to and received from the user. The basebandsub-system 408 can also be connected to a memory 418 that may beconfigured to store data and/or instructions to facilitate the operationof the wireless device 400, and/or to provide storage of information forthe user.

In addition to the aforementioned components, the wireless device mayinclude one or more central processors 420. Each central processor 420may include one or more processor cores. Further, the wireless device400 may include one or more antennas 422A, 422B. In some cases, one ormore of the antennas of the wireless device 400 may be configured totransmit and receive at different frequencies or within differentfrequency ranges. Further, one or more of the antennas may be configuredto work with different wireless networks. Thus, for example, the antenna422A may be configured to transmit and receive signals over a 2Gnetwork, and the antenna 422B may be configured to transmit and receivesignals over a 3G network. In some cases, the antennas 422A and 422B mayboth be configured to transmit and receive signals over, for example, a2.5G network, but at different frequencies.

A number of other wireless device configurations can utilize one or morefeatures described herein. For example, a wireless device does not needto be a multi-band device. In another example, a wireless device caninclude additional antennas such as diversity antenna, and additionalconnectivity features such as Wi-Fi, Bluetooth, and GPS. Further, thewireless device 400 may include any number of additional components,such as analog to digital converters, digital to analog converters,graphics processing units, solid state drives, etc. Moreover, thewireless device 400 can include any type of device that may communicateover one or more wireless networks and that may include a PA 332 and/orPAM 440. For example, the wireless device 400 may be a cellular phone,including a smartphone or a dumbphone, a tablet, a laptop, a video gamedevice, a smart appliance, etc.

Comparison Simulations

Simulations of the bias circuit 100 and the bias circuit 200 wereperformed. The following section compares various characteristics of theoperation of the bias circuit 100 and the bias circuit 200 based on theperformed simulations.

FIG. 5 illustrates a pair of graphs of the voltage at the current source114 for a simulation of the bias circuit 100 and a simulation of thebias circuit 200. The graph 502 on the right represents the bias circuit100 and the graph 504 on the right represents the bias circuit 200. Ascan be seen by the graph 502, the voltage as measured at the currentsource 114 is approximately 2.7 volts. This voltage is the voltage valuepresented to the current source (e.g., at the gate of transistor 208 orthe base of transistor 102). Generally, the battery voltage minus thevoltage presented to the current source is required to be 300 mV ormore. As illustrated in the graph 502, this voltage value appears steadybetween 0 and 5 mA for the current source 114. On the other hand, thevoltage value gradually increases for the bias circuit 200 between 0 and5 mA. However, at its highest point, the voltage of the bias circuit 200at the current source 114 of 5 mA is approximately 2 volts. Thus, in theworst case, the bias circuit 200 reduces the required battery voltage by700 to 800 mV and thus, enables the use of a smaller battery. Forinstance, while the bias circuit 100 may be used with a battery of atleast 3 volts in size, the bias circuit 200 can be used in devices thathave a 2.5 volt battery, or smaller (e.g., 2 to 2.3 volts in somecases).

The voltages measured during the simulations were for a device at 30degrees C. It should be understood that at warmer temperatures, it maybe possible to further reduce the required battery voltage. For example,simulations of the bias circuit 100 at 85 degrees C. resulted in avoltage range measured at the current source 114 of approximately 2.2volts. In comparison, the simulations of the bias circuit 200 at 85degrees C. resulted in a voltage range measured at the current source114 of approximately 1.3 volts with both simulations varying dependingon the process corners used during the simulations. However, for boththe graphs 502 and the graph 504, the worst case is illustrated fortemperature and process corner. Thus, in the worst case, the biascircuit 200 reduced the battery voltage approximately 700 to 800 mVcompared to the bias circuit 100.

FIG. 6 includes a set of graphs illustrating that the feedback loop isstabilized by the RC circuit that includes the resistor 232 and thecapacitor 234. The graph 602 illustrates that the phase margin is above70 degrees. The graphs 604 and 606 are Bode plots that illustrate thatwhen the gain is zero, the phase remains above 45 degrees (e.g.,approximately 75 degrees). The plots 604 and 606 represent the open loopgain and phase around the feedback loop formed by the transistors 110and 208. The phase margin (e.g., the phase shift at unity gain) isevaluated as the bias is swept to ensure acceptable stability margin forthis feedback loop. Typically, anything below 45 degrees is consideredunacceptable. Thus, it is evident from the graphs 604 and 606 that thestability response is acceptable. Further, as the gain reaches 0 atapproximately 100 MHz, the bias circuit 200 will have a bias bandwidthup to approximately 100 MHz.

FIG. 7 illustrates a logarithmic graph 702 comparing the outputimpedance of the bias circuit 100 and the bias circuit 200. The lowerline represents the output impedance of the bias circuit 100. As can beseen from the graph 702, the bias circuit 100 has a low impedance out to10 GHz. The bias circuit 200, the top line on the graph 702, has a lowimpedance up to approximately 20 MHz. However, the impedance begins torise shortly after 20 MHz. Thus, the simulated bias circuit 200 asillustrated may be less effective at higher bandwidths compared to thebias circuit 100. In certain embodiments, it is possible to increase thebandwidth at which the bias circuit 200 is usable.

One solution to improve the bandwidth of the bias circuit 200 is bymodifying the values of the RC circuit in the feedback loop between theamplifier 208 and the transistor 110. Another solution is to addadditional RC circuits in parallel to the RC circuit illustrated in FIG.2. By adding additional RC circuits in parallel, additional zeroes areintroduced into the system that can cancel out poles. This approachenables the bias circuit bandwidth to extend to between 40 and 80 MHz insome cases thereby enabling the bias circuit 200 solution to be used forLong-Term Evolution (LTE) advanced, carrier aggregation, and 5Gcommunications networks, among others.

FIG. 8 illustrates a graph 802 comparing the voltage generated by thebias circuits 100 and 200 for different current values. As with thegraph 702, the top line is for the bias circuit 200 and the bottom lineis for the bias circuit 100. As can be seen from the graph 802, thedifference between the voltages generated by the two bias circuits issmall with the biggest difference at any current value beingapproximately 30 mV.

FIG. 9 illustrates a graph 902 depicting the noise performance of thetwo bias circuits. The top line (beginning from the left of the graph902) represents the bias circuit 100 and the bottom line represents thebias circuit 200. As illustrated by the graph 902, the bias circuit 200has an improved noise performance compared to the bias circuit 100 formost frequencies.

FIG. 10 illustrates a logarithmic graph 1002 comparing the outputimpedance of the bias circuit 100 and the bias circuit 200 as measuredfrom the power amplifier that is in electrical communication with thebias circuits at the node 104. The graph 1002 is similar to the graph702. However, the increasing impedance of the bias circuit 200(represented by the top line in the graph 1002) at higher frequenciesreduced the RF loading. Thus, advantageously, the losses introduced bythe bias circuit on the power amplifier are reduced using the biascircuit 200. In effect, the Schottky diode 202 of the bias circuit 200functions as an inductance or choke at higher frequencies.

FIG. 11 illustrates a graph 1102 illustrating the impact on the biasvoltage as the RF voltage signal increases. Ideally, as the RF signalincreases, the bias voltage should increase. The bias circuit 200 isrepresented by the lower line in the graph 1102. As illustrated by thegraph, modifying the bias circuit as described herein to function with alower battery voltage maintains the desired characteristic of increasingRF energy resulting in increasing bias voltage.

Terminology

Unless the context clearly requires otherwise, throughout thedescription and the claims, the words “comprise,” “comprising,” and thelike are to be construed in an inclusive sense, as opposed to anexclusive or exhaustive sense; that is to say, in the sense of“including, but not limited to.” The term “coupled” is used to refer tothe connection between two elements, the term refers to two or moreelements that may be either directly connected, or connected by way ofone or more intermediate elements. Additionally, the words “herein,”“above,” “below,” and words of similar import, when used in thisapplication, shall refer to this application as a whole and not to anyparticular portions of this application. Where the context permits,words in the above Detailed Description using the singular or pluralnumber may also include the plural or singular number respectively. Theword “or” in reference to a list of two or more items, that word coversall of the following interpretations of the word: any of the items inthe list, all of the items in the list, and any combination of the itemsin the list.

The above detailed description of embodiments of the inventions are notintended to be exhaustive or to limit the inventions to the precise formdisclosed above. While specific embodiments of, and examples for, theinventions are described above for illustrative purposes, variousequivalent modifications are possible within the scope of theinventions, as those skilled in the relevant art will recognize. Forexample, while processes or blocks are presented in a given order,alternative embodiments may perform routines having steps, or employsystems having blocks, in a different order, and some processes orblocks may be deleted, moved, added, subdivided, combined, and/ormodified. Each of these processes or blocks may be implemented in avariety of different ways. Also, while processes or blocks are at timesshown as being performed in series, these processes or blocks mayinstead be performed in parallel, or may be performed at differenttimes.

The teachings of the inventions provided herein can be applied to othersystems, not necessarily the system described above. The elements andacts of the various embodiments described above can be combined toprovide further embodiments.

Conditional language used herein, such as, among others, “can,” “might,”“may,” “e.g.,” and the like, unless specifically stated otherwise, orotherwise understood within the context as used, is generally intendedto convey that certain embodiments include, while other embodiments donot include, certain features, elements and/or states. Thus, suchconditional language is not generally intended to imply that features,elements and/or states are in any way required for one or moreembodiments or that one or more embodiments necessarily include logicfor deciding, with or without author input or prompting, whether thesefeatures, elements and/or states are included or are to be performed inany particular embodiment.

While certain embodiments of the inventions have been described, theseembodiments have been presented by way of example only, and are notintended to limit the scope of the disclosure. Indeed, the novel methodsand systems described herein may be embodied in a variety of otherforms; furthermore, various omissions, substitutions and changes in theform of the methods and systems described herein may be made withoutdeparting from the spirit of the disclosure. The accompanying claims andtheir equivalents are intended to cover such forms or modifications aswould fall within the scope and spirit of the disclosure.

1. (canceled)
 2. A bias circuit comprising: a first Schottky diodeassociated with a first current density; a second Schottky diodeassociated with a second current density; a feedback loop positionedbetween the first Schottky diode and the second Schottky diode, andomitting the first Schottky diode and the second Schottky diode; and afrequency compensation circuit that stabilizes the feedback loop.
 3. Thebias circuit of claim 2 wherein the frequency compensation circuitstabilizes oscillation within the feedback loop.
 4. The bias circuit ofclaim 2 wherein the feedback loop includes a first transistor of a firsttype and a second transistor of a second type.
 5. The bias circuit ofclaim 4 wherein the first transistor is a field effect transistor andthe second transistor is a bipolar junction transistor.
 6. The biascircuit of claim 4 wherein the frequency compensation circuit bisectsthe feedback loop between the first transistor and the secondtransistor.
 7. The bias circuit of claim 2 wherein the frequencycompensation circuit includes a capacitor circuit that compensates forthe Miller effect.
 8. The bias circuit of claim 2 wherein the firstcurrent density matches the second current density.
 9. The bias circuitof claim 2 wherein a size of the first Schottky diode and a size of thesecond Schottky diode are selected such that the first Schottky diodehas a larger area than the second Schottky diode and such that the firstcurrent density matches the second current density.
 10. The bias circuitof claim 2 wherein the bias circuit operates with a battery voltage ofapproximately 2 volts.
 11. The bias circuit of claim 2 wherein the biascircuit operates with a battery voltage of between 1.9 and 2.5 volts.12. The bias circuit of claim 2 further comprising a direct current biascircuit configured to provide a direct current bias to the firstSchottky diode.
 13. The bias circuit of claim 12 wherein the directcurrent bias circuit is formed from a diode and resistor circuit.
 14. Asemiconductor die comprising: a power amplifier; and a bias circuitconfigured to set a quiescent operating point of the power amplifier,the bias circuit including a first Schottky diode associated with afirst current density, a second Schottky diode associated with a secondcurrent density, a feedback loop positioned between the first Schottkydiode and the second Schottky diode, and a frequency compensationcircuit that stabilizes the feedback loop, the feedback loop omittingthe first Schottky diode and the second Schottky diode.
 15. Thesemiconductor die of claim 14 wherein the first transistor is a fieldeffect transistor and the second transistor is a bipolar junctiontransistor.
 16. The semiconductor die of claim 15 wherein the frequencycompensation circuit connects a gate of the field effect transistor to abase of the bipolar junction transistor.
 17. The semiconductor die ofclaim 14 wherein an area of the first Schottky diode is larger than anarea of the second Schottky diode, and the first current densitysubstantially matches the second current density.
 18. The semiconductordie of claim 14 wherein the bias circuit further includes a directcurrent bias circuit that biases the first Schottky diode.
 19. Awireless device comprising: a semiconductor die including a poweramplifier and a bias circuit, the bias circuit configured to set aquiescent operating point of the power amplifier, the bias circuitincluding a first Schottky diode associated with a first currentdensity, a second Schottky diode associated with a second currentdensity, a feedback loop positioned between the first Schottky diode andthe second Schottky diode, and a frequency compensation circuit thatstabilizes the feedback loop, the feedback loop omitting the firstSchottky diode and the second Schottky diode; and an envelope trackerconfigured to control a voltage level of a power amplifier supplyvoltage provided to the power amplifier.
 20. The wireless device ofclaim 19 wherein the first Schottky diode and the second Schottky diodeare sized such that the first current density and the second currentdensity are substantially equal.
 21. The wireless device of claim 19further comprising a reference current circuit configured to provide areference current to the bias circuit.